Architectures for RF

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Architectures for RF Frequency Synthesizers.Kluwer

Architectures for RF Frequency Synthesizers (The Springer International Series in Engineering and Computer Science) (Hardcover)by Cicero S. Vaucher (Author)

Hardcover: 276 pages Publisher: Springer; 1 edition (June 30, 2002) Language: English ISBN-10: 1402071205 ISBN-13: 978-1402071201

Product Description
Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.

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Content

Introduction
1.1 Overview of the Book
References
Tuning System Specifications
Tuning Range
Minimum Step Size
Settling Time
Spurious Signals
Phase Noise Sidebands
Power Dissipation
Integration Level
Interference Generation
References
3 Single-Loop Architectures
Introduction
Integer-N PLL Architecture
PLL Building Blocks

3.3.1
3.3.2
3.3.3
3.3.4
Voltage-Controlled Oscillators
Frequency Dividers
Phase Detectors
The Phase-Frequency Detector/Charge-Pump Combination
Loop Filter
Dimensioning of the PLL Parameters
Open- and Closed-loop Transfer Functions
Open-loop Bandwidth and Phase Margin
Spectral Purity Performance
Spurious Reference Breakthrough
Phase Noise Performance
Design of the Loop Filter
Spurious Reference Breakthrough
Phase Noise Contribution from the Loop Filter Resistor
Dimensioning of Time Constant and Capacitance
The Choice of the Reference Frequency
Single loop PLL with Divided Oscillator Output
Fractional-N PLL Techniques
Phase Error Compensation
Modulation Techniques
Translation Loops
Direct Digital Frequency Synthesizers
Architectures Combining PLL and DDS Synthesizers
Summary of Conclusions on Single-Loop Architectures
References
4 Wide-Band Architectures
Introduction
Receiver Architectures
Residual Phase Deviation
The Residual Phase Deviation Power
The Open-Loop Bandwidth for Optimum Phase Noise
Performance
Minimum Approximated Residual Phase Deviation
Influence of the Phase Margin on the Residual Phase
Deviation
The Influence of the Open-Loop Bandwidth on the
Residual Phase Deviation
The Condition for the Implementation of the Optimum
Loop Bandwidth
Single-Loop Design
Specification of the PLL Building Blocks
Single-Loop Architectures
Wide-Band Loop Design
Multi-Loop Design
Phase Noise Performance
Specification of the Different Loops
The Limiting Values for the Reference Frequency
Satellite Tuning System
Double-loop Tuning System Architecture
Phase Noise Performance
Dividers in Bipolar Technology
Architecture
Logic Implementation of the Divider Cells
Circuit Implementation
Power Dissipation Optimization and Sensitivity Measurements
VHF PFD/CP Architectures
Architecture
Circuit Implementation
Measurement Results
Conclusions
References
5 Adaptive PLL Architecture
Introduction
RDS Car-Radio Application
Multi-Band Tuner Architecture
Settling Time
Settling Behaviour
Open-Loop Bandwidth, Phase Margin and Settling
Time Specifications
5.5 Settling Time Requirements
5.6 Residual Frequency Deviation
Introduction
Basic Concepts
Simplified Treatment of the Residual Frequency Deviation
of a PLL
Numerical Results with Analytic Transfer Functions .
Conclusions
Terrestrial FM Broadcasting
Reference Spurious Signals and Loop Filter Attenuation
Limitations of Existing PLL Architectures
Adaptive PLL Architecture
Basic Architecture
Loop Filter Implementation
Dead-Zone Implementation
Circuit Implementation
Programmable Dividers
Oscillators
Charge-Pumps
Measurements
Conclusions
References
6 Programmable Dividers
Introduction
Divider Architectures
Architecture Based on a Dual-Modulus Prescaler
Presettable Programmable Counters
Basic Programmable Prescaler
Adaptive Power Prescaler Architecture for Multi-Band
Applications
Prescaler with Extended Programmability
Dividers in CMOS Technology
Logic Implementation of the Divider Cells
Circuit Implementation of the Divider Cells
Power Dissipation Optimization
Input Amplifier
Input Sensitivity Measurements and Maximum Operation
Frequencies
Phase Noise Measurements
Conclusions
References
7 Conclusions
A PLL Stability Limits Due to the Discrete-Time PFD/CP Operation 237
A.1 Stability Limits
References
B Clock-Conversion PLLs for Optical Transmitters
References

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:11bb :11bb :11bb :11bb :11bb
很好的书，谢谢！

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