Architectures for RF

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Architectures for RF Frequency Synthesizers.Kluwer

Architectures for RF Frequency Synthesizers (The Springer International Series in Engineering and Computer Science) (Hardcover)by Cicero S. Vaucher (Author)g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
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Hardcover: 276 pages Publisher: Springer; 1 edition (June 30, 2002) Language: English ISBN-10: 1402071205 ISBN-13: 978-1402071201 g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
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Product Descriptiong¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
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    Contentg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Introductiong¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    1.1 Overview of the Bookg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Referencesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Tuning System Specificationsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Tuning Rangeg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Minimum Step Sizeg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Settling Timeg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Spurious Signalsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Phase Noise Sidebandsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Power Dissipationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Integration Levelg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Interference Generationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Referencesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    3 Single-Loop Architecturesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Introductiong¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Integer-N PLL Architectureg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    PLL Building Blocksg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    3.3.1g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    3.3.2g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    3.3.3g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    3.3.4g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Voltage-Controlled Oscillatorsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Frequency Dividersg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Phase Detectorsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    The Phase-Frequency Detector/Charge-Pump Combinationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Loop Filterg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Dimensioning of the PLL Parametersg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Open- and Closed-loop Transfer Functionsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Open-loop Bandwidth and Phase Marging¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Spectral Purity Performanceg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Spurious Reference Breakthroughg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Phase Noise Performanceg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Design of the Loop Filterg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Spurious Reference Breakthroughg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Phase Noise Contribution from the Loop Filter Resistorg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Dimensioning of Time Constant and Capacitanceg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    The Choice of the Reference Frequencyg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Single loop PLL with Divided Oscillator Outputg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Fractional-N PLL Techniquesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Phase Error Compensationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Modulation Techniquesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Translation Loopsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Direct Digital Frequency Synthesizersg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Architectures Combining PLL and DDS Synthesizersg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Summary of Conclusions on Single-Loop Architecturesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Referencesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    4 Wide-Band Architecturesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Introductiong¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Receiver Architecturesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Residual Phase Deviationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    The Residual Phase Deviation Powerg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    The Open-Loop Bandwidth for Optimum Phase Noiseg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Performanceg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Minimum Approximated Residual Phase Deviationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Influence of the Phase Margin on the Residual Phaseg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Deviationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    The Influence of the Open-Loop Bandwidth on theg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Residual Phase Deviationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    The Condition for the Implementation of the Optimumg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Loop Bandwidthg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Single-Loop Designg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Specification of the PLL Building Blocksg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Single-Loop Architecturesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Wide-Band Loop Designg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Multi-Loop Designg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Phase Noise Performanceg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Specification of the Different Loopsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    The Limiting Values for the Reference Frequencyg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Satellite Tuning Systemg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Double-loop Tuning System Architectureg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Phase Noise Performanceg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Dividers in Bipolar Technologyg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Architectureg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Logic Implementation of the Divider Cellsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Circuit Implementationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Power Dissipation Optimization and Sensitivity Measurementsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    VHF PFD/CP Architecturesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Architectureg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Circuit Implementationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Measurement Resultsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Conclusionsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Referencesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    5 Adaptive PLL Architectureg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Introductiong¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    RDS Car-Radio Applicationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Multi-Band Tuner Architectureg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Settling Timeg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Settling Behaviourg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Open-Loop Bandwidth, Phase Margin and Settlingg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Time Specificationsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    5.5 Settling Time Requirementsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    5.6 Residual Frequency Deviationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Introductiong¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Basic Conceptsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Simplified Treatment of the Residual Frequency Deviationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    of a PLLg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Numerical Results with Analytic Transfer Functions .g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Conclusionsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Terrestrial FM Broadcastingg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Reference Spurious Signals and Loop Filter Attenuationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Limitations of Existing PLL Architecturesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Adaptive PLL Architectureg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Basic Architectureg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Loop Filter Implementationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Dead-Zone Implementationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Circuit Implementationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Programmable Dividersg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Oscillatorsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Charge-Pumpsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Measurementsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Conclusionsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Referencesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    6 Programmable Dividersg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Introductiong¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Divider Architecturesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Architecture Based on a Dual-Modulus Prescalerg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Presettable Programmable Countersg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Basic Programmable Prescalerg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Adaptive Power Prescaler Architecture for Multi-Bandg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Applicationsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Prescaler with Extended Programmabilityg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Dividers in CMOS Technologyg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Logic Implementation of the Divider Cellsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Circuit Implementation of the Divider Cellsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Power Dissipation Optimizationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Input Amplifierg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Input Sensitivity Measurements and Maximum Operationg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Frequenciesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Phase Noise Measurementsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Conclusionsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Referencesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    7 Conclusionsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    A PLL Stability Limits Due to the Discrete-Time PFD/CP Operation 237g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    A.1 Stability Limitsg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Referencesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    B Clock-Conversion PLLs for Optical Transmittersg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    Referencesg¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
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    Architectures for RF Frequency Synthesizers.Kluwer.part7g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
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    :11bb :11bb :11bb :11bb :11bb g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
    很好的书,谢谢!g¦»·} DÎúimw.mwhrf.com(a,Vþ8‹b
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